Smart cards include memory elements dedicated to the storage of information, such as information on the identity of an individual (for example the name, address etc) or relating to administrative data for an individual (for example social security number, bank reference etc.). Smart cards also include processing circuits for performing operations on the data stored in said memory elements, conjointly with the data sent by a smart card reader. This is particularly the case in certain operations of the bank transaction type in which the smart card becomes a separate data processing unit. For the processing of data performed in parallel between the smart card reader and the smart card to be possible, the smart card reader supplies a clock signal to the smart card. The purpose of this clock signal is to time the digital processing circuits disposed on the smart card.
In a known fashion, FIG. 1 depicts a device 101 for generating an output clock signal 102. The generating device 101 is disposed in a smart card reader 103. Said output clock signal 102 is applied to the smart card 104 when the latter is in read or write configuration allowing dialogue 105 with the smart card reader.
The generating device 101 receives an input clock signal 106 delivered by the internal clock of the microprocessor 107 and responsible for the various processing operations on the smart card reader. In order to adapt the frequency of the output clock signal 102 to the processing characteristics of the smart card 104, a frequency divider 108 receives the input clock signal 106 at its input and delivers a clock signal 109, referred to as the first clock signal, which has undergone a frequency division. The frequency of the input clock signal 106 is thus divided by a factor of 1, 2, 4 or 8, depending on the value of a control signal 110. The signal 109 is amplified by the stage 111, which delivers said output clock signal 102.
The device described in FIG. 1 has many functional limitations, in particular when said first clock signal 106 received by the generating device 101 stops.
Actually, such a generating device does not make it possible to deliver an output clock signal 102 when the input clock signal 106 delivered by the microprocessor 107 stops. The stoppage of the input clock signal 106 delivered by the microprocessor can in particular occur following a drop in the supply voltage to said microprocessor. When this occurs, the input clock signal 106 remains either at a high binary level or at a low binary level. The consequence of this is that the first clock signal 109 and the output clock signal 102 remain respectively either at a high binary level or at a low binary level, which risks damaging the processing circuits of the smart card which are timed by the output clock signal 102. In addition, the processing operations being executed on the smart card are abruptly stopped, which may result in the storage of erroneous data in the memory elements of the smart card.